// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Fast Corner delays for the design using part EP4CE22F17C6,
// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "DE0_NANO")
  (DATE "08/09/2018 00:24:51")
  (VENDOR "Altera")
  (PROGRAM "Quartus Prime")
  (VERSION "Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[0\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (772:772:772) (803:803:803))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[1\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (772:772:772) (803:803:803))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[5\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1682:1682:1682) (1908:1908:1908))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[7\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1349:1349:1349) (1523:1523:1523))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[9\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1706:1706:1706) (1932:1932:1932))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[11\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1219:1219:1219) (1374:1374:1374))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[13\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1398:1398:1398) (1566:1566:1566))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[15\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1154:1154:1154) (1311:1311:1311))
        (IOPATH i o (3177:3177:3177) (2883:2883:2883))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[17\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1383:1383:1383) (1589:1589:1589))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[19\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (931:931:931) (1050:1050:1050))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[21\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1035:1035:1035) (1172:1172:1172))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[23\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (893:893:893) (995:995:995))
        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE CLOCK_50\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (704:704:704))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_pll")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|pll1)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1114:1114:1114) (1114:1114:1114))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1141:1141:1141) (1136:1136:1136))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1141:1141:1141) (1136:1136:1136))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[0\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (153:153:153) (208:208:208))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[1\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (157:157:157) (211:211:211))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[2\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT datab (158:158:158) (213:213:213))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[0\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (147:147:147) (197:197:197))
        (IOPATH datab combout (192:192:192) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[1\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (147:147:147) (199:199:199))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[2\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (147:147:147) (198:198:198))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[3\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (147:147:147) (197:197:197))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[4\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (217:217:217) (281:281:281))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[5\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (152:152:152) (204:204:204))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[6\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT datab (150:150:150) (201:201:201))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[7\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (165:165:165) (218:218:218))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[8\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (218:218:218) (283:283:283))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[9\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT dataa (151:151:151) (207:207:207))
        (IOPATH dataa combout (195:195:195) (203:203:203))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (917:917:917))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (334:334:334) (388:388:388))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (221:221:221) (287:287:287))
        (PORT datab (147:147:147) (197:197:197))
        (PORT datac (140:140:140) (187:187:187))
        (PORT datad (134:134:134) (173:173:173))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (161:161:161) (167:167:167))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT datac (134:134:134) (177:177:177))
        (PORT datad (136:136:136) (175:175:175))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (218:218:218) (282:282:282))
        (PORT datab (154:154:154) (206:206:206))
        (PORT datac (152:152:152) (198:198:198))
        (PORT datad (140:140:140) (181:181:181))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE KEY\[0\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT dataa (107:107:107) (139:139:139))
        (PORT datab (102:102:102) (131:131:131))
        (PORT datac (93:93:93) (115:115:115))
        (PORT datad (1959:1959:1959) (2208:2208:2208))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[3\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (161:161:161) (216:216:216))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[4\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[5\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[6\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[7\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (194:194:194))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[8\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT datab (145:145:145) (195:195:195))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~30)
    (DELAY
      (ABSOLUTE
        (PORT dataa (146:146:146) (199:199:199))
        (IOPATH dataa combout (195:195:195) (203:203:203))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~1)
    (DELAY
      (ABSOLUTE
        (PORT datac (331:331:331) (393:393:393))
        (PORT datad (320:320:320) (382:382:382))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal1\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (358:358:358) (434:434:434))
        (PORT datac (328:328:328) (390:390:390))
        (PORT datad (314:314:314) (373:373:373))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal1\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (344:344:344) (418:418:418))
        (PORT datab (337:337:337) (408:408:408))
        (PORT datac (328:328:328) (392:392:392))
        (PORT datad (95:95:95) (114:114:114))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (339:339:339) (411:411:411))
        (PORT datad (315:315:315) (373:373:373))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (178:178:178) (221:221:221))
        (PORT datab (103:103:103) (131:131:131))
        (PORT datac (90:90:90) (111:111:111))
        (PORT datad (2094:2094:2094) (2379:2379:2379))
        (IOPATH dataa combout (166:166:166) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (576:576:576) (666:666:666))
        (PORT ena (761:761:761) (821:821:821))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (337:337:337) (410:410:410))
        (PORT datab (337:337:337) (406:406:406))
        (PORT datac (330:330:330) (394:394:394))
        (PORT datad (316:316:316) (374:374:374))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (343:343:343) (416:416:416))
        (PORT datab (358:358:358) (434:434:434))
        (PORT datac (329:329:329) (391:391:391))
        (PORT datad (314:314:314) (372:372:372))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (105:105:105) (137:137:137))
        (PORT datab (103:103:103) (131:131:131))
        (PORT datac (328:328:328) (389:389:389))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|H_SYNC_NEG\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (218:218:218) (281:281:281))
        (PORT datab (153:153:153) (206:206:206))
        (PORT datac (152:152:152) (198:198:198))
        (PORT datad (140:140:140) (181:181:181))
        (IOPATH dataa combout (159:159:159) (173:173:173))
        (IOPATH datab combout (161:161:161) (174:174:174))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|H_SYNC_NEG\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (221:221:221) (286:286:286))
        (PORT datab (101:101:101) (130:130:130))
        (PORT datac (140:140:140) (187:187:187))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (120:120:120) (125:125:125))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[9\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (334:334:334) (406:406:406))
        (PORT datab (249:249:249) (311:311:311))
        (PORT datac (330:330:330) (394:394:394))
        (PORT datad (238:238:238) (299:299:299))
        (IOPATH dataa combout (195:195:195) (193:193:193))
        (IOPATH datab combout (188:188:188) (177:177:177))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[8\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (337:337:337) (410:410:410))
        (PORT datab (253:253:253) (315:315:315))
        (PORT datac (330:330:330) (394:394:394))
        (PORT datad (240:240:240) (301:301:301))
        (IOPATH dataa combout (188:188:188) (179:179:179))
        (IOPATH datab combout (196:196:196) (192:192:192))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (333:333:333) (405:405:405))
        (PORT datab (247:247:247) (309:309:309))
        (PORT datac (329:329:329) (393:393:393))
        (PORT datad (237:237:237) (298:298:298))
        (IOPATH dataa combout (195:195:195) (193:193:193))
        (IOPATH datab combout (196:196:196) (193:193:193))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (165:165:165) (220:220:220))
        (PORT datad (148:148:148) (193:193:193))
        (IOPATH datab combout (167:167:167) (167:167:167))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[10\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (164:164:164) (220:220:220))
        (PORT datac (142:142:142) (190:190:190))
        (PORT datad (147:147:147) (192:192:192))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[6\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (332:332:332) (404:404:404))
        (PORT datab (256:256:256) (322:322:322))
        (PORT datac (329:329:329) (393:393:393))
        (IOPATH dataa combout (195:195:195) (193:193:193))
        (IOPATH datab combout (196:196:196) (192:192:192))
        (IOPATH datac combout (120:120:120) (125:125:125))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT datac (329:329:329) (393:393:393))
        (PORT datad (237:237:237) (298:298:298))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[9\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (153:153:153) (207:207:207))
        (PORT datab (163:163:163) (219:219:219))
        (PORT datac (142:142:142) (189:189:189))
        (PORT datad (147:147:147) (192:192:192))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (190:190:190) (177:177:177))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[8\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (152:152:152) (207:207:207))
        (PORT datab (163:163:163) (219:219:219))
        (PORT datac (142:142:142) (189:189:189))
        (PORT datad (146:146:146) (192:192:192))
        (IOPATH dataa combout (181:181:181) (193:193:193))
        (IOPATH datab combout (192:192:192) (188:188:188))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (175:175:175) (217:217:217))
        (PORT datab (331:331:331) (394:394:394))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (105:105:105) (136:136:136))
        (PORT datab (266:266:266) (309:309:309))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (175:175:175) (218:218:218))
        (PORT datab (104:104:104) (134:134:134))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (105:105:105) (136:136:136))
        (PORT datab (189:189:189) (228:228:228))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8)
    (DELAY
      (ABSOLUTE
        (PORT datab (102:102:102) (131:131:131))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (102:102:102) (131:131:131))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[2\]\[5\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT datac (135:135:135) (179:179:179))
        (PORT datad (135:135:135) (175:175:175))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (333:333:333) (402:402:402))
        (PORT datab (176:176:176) (217:217:217))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (284:284:284) (333:333:333))
        (PORT datab (270:270:270) (312:312:312))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[7\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (338:338:338) (410:410:410))
        (PORT datab (351:351:351) (422:422:422))
        (PORT datac (321:321:321) (385:385:385))
        (PORT datad (314:314:314) (372:372:372))
        (IOPATH dataa combout (181:181:181) (184:184:184))
        (IOPATH datab combout (191:191:191) (188:188:188))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[6\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (338:338:338) (410:410:410))
        (PORT datac (320:320:320) (384:384:384))
        (PORT datad (313:313:313) (371:371:371))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[5\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT datac (320:320:320) (384:384:384))
        (PORT datad (324:324:324) (382:382:382))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (382:382:382) (462:462:462))
        (PORT datab (332:332:332) (399:399:399))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (186:186:186) (221:221:221))
        (PORT datab (392:392:392) (470:470:470))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (378:378:378) (460:460:460))
        (PORT datab (171:171:171) (205:205:205))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (188:188:188) (224:224:224))
        (PORT datab (392:392:392) (470:470:470))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (176:176:176) (219:219:219))
        (PORT datab (386:386:386) (470:470:470))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (194:194:194) (234:234:234))
        (PORT datab (377:377:377) (459:459:459))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (176:176:176) (219:219:219))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~14)
    (DELAY
      (ABSOLUTE
        (PORT datab (190:190:190) (229:229:229))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (105:105:105) (134:134:134))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (104:104:104) (133:133:133))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|address_reg_b\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (913:913:913))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[32\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[33\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (132:132:132) (176:176:176))
        (PORT datad (1760:1760:1760) (1968:1968:1968))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE is_lsb\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (103:103:103) (121:121:121))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE is_lsb)
    (DELAY
      (ABSOLUTE
        (PORT clk (981:981:981) (1070:1070:1070))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[0\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (222:222:222) (279:279:279))
        (PORT datab (554:554:554) (655:655:655))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE last_href\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (1758:1758:1758) (1966:1966:1966))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE last_href)
    (DELAY
      (ABSOLUTE
        (PORT clk (981:981:981) (1070:1070:1070))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[30\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[13\]\~43)
    (DELAY
      (ABSOLUTE
        (PORT datab (150:150:150) (201:201:201))
        (PORT datac (1796:1796:1796) (2009:2009:2009))
        (PORT datad (1754:1754:1754) (1962:1962:1962))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[1\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (141:141:141) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (142:142:142) (193:193:193))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[3\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[4\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[5\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[6\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[7\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[8\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[9\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[10\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[11\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[12\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (194:194:194))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[13\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT datab (141:141:141) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[0\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (498:498:498) (589:589:589))
        (PORT datab (157:157:157) (212:212:212))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE always0\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (149:149:149) (200:200:200))
        (PORT datac (1796:1796:1796) (2009:2009:2009))
        (PORT datad (1755:1755:1755) (1962:1962:1962))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[1\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (165:165:165) (223:223:223))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (167:167:167) (228:228:228))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[3\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (161:161:161) (216:216:216))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[4\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[5\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[6\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (191:191:191))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[7\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (191:191:191))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[9\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (385:385:385) (464:464:464))
        (PORT datab (380:380:380) (457:457:457))
        (PORT datac (368:368:368) (439:439:439))
        (PORT datad (376:376:376) (455:455:455))
        (IOPATH dataa combout (195:195:195) (193:193:193))
        (IOPATH datab combout (188:188:188) (177:177:177))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[8\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (385:385:385) (464:464:464))
        (PORT datab (380:380:380) (457:457:457))
        (PORT datac (369:369:369) (439:439:439))
        (PORT datad (375:375:375) (454:454:454))
        (IOPATH dataa combout (181:181:181) (193:193:193))
        (IOPATH datab combout (192:192:192) (188:188:188))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|_\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (378:378:378) (456:456:456))
        (PORT datac (367:367:367) (446:446:446))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (385:385:385) (464:464:464))
        (PORT datab (380:380:380) (457:457:457))
        (PORT datac (369:369:369) (439:439:439))
        (PORT datad (376:376:376) (454:454:454))
        (IOPATH dataa combout (192:192:192) (184:184:184))
        (IOPATH datab combout (182:182:182) (193:193:193))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[6\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (384:384:384) (464:464:464))
        (PORT datac (365:365:365) (436:436:436))
        (PORT datad (376:376:376) (454:454:454))
        (IOPATH dataa combout (195:195:195) (203:203:203))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[10\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (163:163:163) (219:219:219))
        (PORT datac (154:154:154) (208:208:208))
        (PORT datad (157:157:157) (207:207:207))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[9\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (163:163:163) (225:225:225))
        (PORT datab (159:159:159) (214:214:214))
        (PORT datac (146:146:146) (199:199:199))
        (PORT datad (142:142:142) (184:184:184))
        (IOPATH dataa combout (195:195:195) (193:193:193))
        (IOPATH datab combout (188:188:188) (177:177:177))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (385:385:385) (461:461:461))
        (PORT datad (375:375:375) (454:454:454))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[8\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (172:172:172) (233:233:233))
        (PORT datab (164:164:164) (219:219:219))
        (PORT datac (154:154:154) (208:208:208))
        (PORT datad (149:149:149) (193:193:193))
        (IOPATH dataa combout (181:181:181) (193:193:193))
        (IOPATH datab combout (192:192:192) (188:188:188))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (400:400:400) (483:483:483))
        (PORT datab (334:334:334) (390:390:390))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (335:335:335) (389:389:389))
        (PORT datab (103:103:103) (132:132:132))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (104:104:104) (135:135:135))
        (PORT datab (336:336:336) (391:391:391))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (336:336:336) (392:392:392))
        (PORT datab (103:103:103) (132:132:132))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8)
    (DELAY
      (ABSOLUTE
        (PORT datab (104:104:104) (133:133:133))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (104:104:104) (132:132:132))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[8\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[9\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[2\]\[5\])
    (DELAY
      (ABSOLUTE
        (PORT datac (530:530:530) (632:632:632))
        (PORT datad (531:531:531) (627:627:627))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (366:366:366) (444:444:444))
        (PORT datab (102:102:102) (130:130:130))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (103:103:103) (133:133:133))
        (PORT datab (172:172:172) (210:210:210))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[7\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (173:173:173) (234:234:234))
        (PORT datab (164:164:164) (220:220:220))
        (PORT datac (155:155:155) (209:209:209))
        (PORT datad (150:150:150) (193:193:193))
        (IOPATH dataa combout (195:195:195) (193:193:193))
        (IOPATH datab combout (196:196:196) (193:193:193))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[6\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (173:173:173) (234:234:234))
        (PORT datac (156:156:156) (210:210:210))
        (PORT datad (150:150:150) (194:194:194))
        (IOPATH dataa combout (195:195:195) (203:203:203))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT datac (369:369:369) (443:443:443))
        (PORT datad (358:358:358) (427:427:427))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (391:391:391) (466:466:466))
        (PORT datab (343:343:343) (407:407:407))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (226:226:226) (280:280:280))
        (PORT datab (102:102:102) (131:131:131))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (335:335:335) (391:391:391))
        (PORT datab (336:336:336) (402:402:402))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (212:212:212) (266:266:266))
        (PORT datab (355:355:355) (420:420:420))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (350:350:350) (424:424:424))
        (PORT datab (189:189:189) (228:228:228))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (298:298:298) (347:347:347))
        (PORT datab (223:223:223) (276:276:276))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (352:352:352) (419:419:419))
        (PORT datab (173:173:173) (212:212:212))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (348:348:348) (412:412:412))
        (PORT datab (190:190:190) (229:229:229))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (228:228:228) (281:281:281))
        (PORT datab (287:287:287) (334:334:334))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (326:326:326) (388:388:388))
        (PORT datab (175:175:175) (215:215:215))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (166:166:166) (174:174:174))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[14\]\~44)
    (DELAY
      (ABSOLUTE
        (PORT dataa (142:142:142) (193:193:193))
        (IOPATH dataa combout (188:188:188) (193:193:193))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (1084:1084:1084))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (2289:2289:2289) (2111:2111:2111))
        (PORT ena (806:806:806) (876:876:876))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[10\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (188:188:188) (193:193:193))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (978:978:978) (1059:1059:1059))
        (PORT d (37:37:37) (50:50:50))
        (PORT sclr (555:555:555) (640:640:640))
        (PORT ena (2329:2329:2329) (2131:2131:2131))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD sclr (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[2\]\[6\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (547:547:547) (649:649:649))
        (PORT datac (527:527:527) (629:629:629))
        (PORT datad (515:515:515) (607:607:607))
        (IOPATH datab combout (167:167:167) (174:174:174))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[10\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (385:385:385) (464:464:464))
        (PORT datac (368:368:368) (439:439:439))
        (PORT datad (363:363:363) (433:433:433))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12)
    (DELAY
      (ABSOLUTE
        (PORT datad (91:91:91) (109:109:109))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (326:326:326) (390:390:390))
        (PORT datad (90:90:90) (107:107:107))
        (IOPATH dataa combout (188:188:188) (193:193:193))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (206:206:206) (259:259:259))
        (PORT datad (271:271:271) (310:310:310))
        (IOPATH datab combout (188:188:188) (193:193:193))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE W_EN\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (135:135:135) (179:179:179))
        (PORT datad (1754:1754:1754) (1962:1962:1962))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE W_EN\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (105:105:105) (122:122:122))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE W_EN)
    (DELAY
      (ABSOLUTE
        (PORT clk (981:981:981) (1070:1070:1070))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode300w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (120:120:120) (155:155:155))
        (PORT datac (106:106:106) (135:135:135))
        (PORT datad (528:528:528) (625:625:625))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1141:1141:1141) (1136:1136:1136))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[10\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (248:248:248) (310:310:310))
        (PORT datac (317:317:317) (380:380:380))
        (PORT datad (237:237:237) (298:298:298))
        (IOPATH datab combout (191:191:191) (181:181:181))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12)
    (DELAY
      (ABSOLUTE
        (PORT datad (91:91:91) (109:109:109))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (174:174:174) (215:215:215))
        (PORT datab (190:190:190) (230:230:230))
        (IOPATH dataa combout (188:188:188) (203:203:203))
        (IOPATH datab combout (190:190:190) (205:205:205))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (105:105:105) (134:134:134))
        (IOPATH datab combout (188:188:188) (193:193:193))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode338w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (196:196:196) (233:233:233))
        (PORT datad (192:192:192) (224:224:224))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[27\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[7\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (1972:1972:1972) (2201:2201:2201))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1161:1161:1161) (1269:1269:1269))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (659:659:659) (712:712:712))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (975:975:975) (1165:1165:1165))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1115:1115:1115) (1315:1315:1315))
        (PORT d[1] (1568:1568:1568) (1838:1838:1838))
        (PORT d[2] (1744:1744:1744) (2010:2010:2010))
        (PORT d[3] (704:704:704) (819:819:819))
        (PORT d[4] (945:945:945) (1085:1085:1085))
        (PORT d[5] (608:608:608) (700:700:700))
        (PORT d[6] (920:920:920) (1065:1065:1065))
        (PORT d[7] (1525:1525:1525) (1752:1752:1752))
        (PORT d[8] (739:739:739) (851:851:851))
        (PORT d[9] (750:750:750) (861:861:861))
        (PORT d[10] (793:793:793) (904:904:904))
        (PORT d[11] (1812:1812:1812) (2075:2075:2075))
        (PORT d[12] (1108:1108:1108) (1272:1272:1272))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1422:1422:1422) (1586:1586:1586))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (PORT d[0] (1706:1706:1706) (1879:1879:1879))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1011:1011:1011) (1164:1164:1164))
        (PORT d[1] (888:888:888) (1039:1039:1039))
        (PORT d[2] (870:870:870) (1016:1016:1016))
        (PORT d[3] (897:897:897) (1046:1046:1046))
        (PORT d[4] (1177:1177:1177) (1348:1348:1348))
        (PORT d[5] (1241:1241:1241) (1415:1415:1415))
        (PORT d[6] (1069:1069:1069) (1213:1213:1213))
        (PORT d[7] (1204:1204:1204) (1397:1397:1397))
        (PORT d[8] (1248:1248:1248) (1423:1423:1423))
        (PORT d[9] (999:999:999) (1143:1143:1143))
        (PORT d[10] (1109:1109:1109) (1274:1274:1274))
        (PORT d[11] (991:991:991) (1135:1135:1135))
        (PORT d[12] (1009:1009:1009) (1160:1160:1160))
        (PORT clk (1048:1048:1048) (1067:1067:1067))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1067:1067:1067))
        (PORT d[0] (952:952:952) (1054:1054:1054))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode313w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (121:121:121) (155:155:155))
        (PORT datac (106:106:106) (135:135:135))
        (PORT datad (528:528:528) (625:625:625))
        (IOPATH datab combout (166:166:166) (167:167:167))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode352w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (197:197:197) (233:233:233))
        (PORT datad (192:192:192) (224:224:224))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (845:845:845) (1011:1011:1011))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1323:1323:1323) (1550:1550:1550))
        (PORT d[1] (1560:1560:1560) (1830:1830:1830))
        (PORT d[2] (1737:1737:1737) (2003:2003:2003))
        (PORT d[3] (726:726:726) (848:848:848))
        (PORT d[4] (771:771:771) (890:890:890))
        (PORT d[5] (636:636:636) (734:734:734))
        (PORT d[6] (724:724:724) (844:844:844))
        (PORT d[7] (789:789:789) (906:906:906))
        (PORT d[8] (626:626:626) (722:722:722))
        (PORT d[9] (1101:1101:1101) (1257:1257:1257))
        (PORT d[10] (652:652:652) (749:749:749))
        (PORT d[11] (1617:1617:1617) (1846:1846:1846))
        (PORT d[12] (1092:1092:1092) (1254:1254:1254))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1443:1443:1443) (1588:1588:1588))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (PORT d[0] (1727:1727:1727) (1881:1881:1881))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (853:853:853) (991:991:991))
        (PORT d[1] (725:725:725) (856:856:856))
        (PORT d[2] (1064:1064:1064) (1241:1241:1241))
        (PORT d[3] (1085:1085:1085) (1270:1270:1270))
        (PORT d[4] (1337:1337:1337) (1526:1526:1526))
        (PORT d[5] (1258:1258:1258) (1438:1438:1438))
        (PORT d[6] (1080:1080:1080) (1230:1230:1230))
        (PORT d[7] (906:906:906) (1033:1033:1033))
        (PORT d[8] (1398:1398:1398) (1595:1595:1595))
        (PORT d[9] (1305:1305:1305) (1501:1501:1501))
        (PORT d[10] (1363:1363:1363) (1555:1555:1555))
        (PORT d[11] (831:831:831) (952:952:952))
        (PORT d[12] (1151:1151:1151) (1320:1320:1320))
        (PORT clk (1048:1048:1048) (1067:1067:1067))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1067:1067:1067))
        (PORT d[0] (949:949:949) (1061:1061:1061))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|address_reg_b\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (913:913:913))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (695:695:695) (841:841:841))
        (PORT datab (543:543:543) (625:625:625))
        (PORT datac (630:630:630) (718:718:718))
        (PORT datad (542:542:542) (653:653:653))
        (IOPATH dataa combout (188:188:188) (179:179:179))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode321w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (116:116:116) (150:150:150))
        (PORT datac (101:101:101) (129:129:129))
        (PORT datad (532:532:532) (630:630:630))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode361w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (101:101:101) (122:122:122))
        (PORT datad (102:102:102) (119:119:119))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (853:853:853) (1023:1023:1023))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (935:935:935) (1110:1110:1110))
        (PORT d[1] (1385:1385:1385) (1633:1633:1633))
        (PORT d[2] (1716:1716:1716) (1978:1978:1978))
        (PORT d[3] (756:756:756) (886:886:886))
        (PORT d[4] (791:791:791) (918:918:918))
        (PORT d[5] (661:661:661) (766:766:766))
        (PORT d[6] (746:746:746) (871:871:871))
        (PORT d[7] (1344:1344:1344) (1543:1543:1543))
        (PORT d[8] (659:659:659) (766:766:766))
        (PORT d[9] (1111:1111:1111) (1273:1273:1273))
        (PORT d[10] (673:673:673) (773:773:773))
        (PORT d[11] (1618:1618:1618) (1852:1852:1852))
        (PORT d[12] (946:946:946) (1089:1089:1089))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1239:1239:1239) (1382:1382:1382))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (1523:1523:1523) (1675:1675:1675))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (823:823:823) (948:948:948))
        (PORT d[1] (1071:1071:1071) (1248:1248:1248))
        (PORT d[2] (1077:1077:1077) (1257:1257:1257))
        (PORT d[3] (1085:1085:1085) (1268:1268:1268))
        (PORT d[4] (1359:1359:1359) (1553:1553:1553))
        (PORT d[5] (1270:1270:1270) (1452:1452:1452))
        (PORT d[6] (1115:1115:1115) (1276:1276:1276))
        (PORT d[7] (1173:1173:1173) (1353:1353:1353))
        (PORT d[8] (1425:1425:1425) (1630:1630:1630))
        (PORT d[9] (1177:1177:1177) (1348:1348:1348))
        (PORT d[10] (1417:1417:1417) (1617:1617:1617))
        (PORT d[11] (1174:1174:1174) (1348:1348:1348))
        (PORT d[12] (1161:1161:1161) (1332:1332:1332))
        (PORT clk (1049:1049:1049) (1069:1069:1069))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1069:1069:1069))
        (PORT d[0] (747:747:747) (826:826:826))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode329w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (116:116:116) (150:150:150))
        (PORT datac (101:101:101) (129:129:129))
        (PORT datad (532:532:532) (630:630:630))
        (IOPATH datab combout (167:167:167) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode370w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (195:195:195) (232:232:232))
        (PORT datad (191:191:191) (223:223:223))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[23\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (1827:1827:1827) (2047:2047:2047))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1143:1143:1143) (1240:1240:1240))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (678:678:678) (745:745:745))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[24\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (1874:1874:1874) (2093:2093:2093))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1143:1143:1143) (1240:1240:1240))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (678:678:678) (745:745:745))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[20\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1161:1161:1161) (1269:1269:1269))
        (PORT asdata (2148:2148:2148) (2384:2384:2384))
        (PORT ena (659:659:659) (712:712:712))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[21\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1161:1161:1161) (1269:1269:1269))
        (PORT asdata (1979:1979:1979) (2184:2184:2184))
        (PORT ena (659:659:659) (712:712:712))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[22\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (704:704:704))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[4\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (2006:2006:2006) (2287:2287:2287))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1161:1161:1161) (1269:1269:1269))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (659:659:659) (712:712:712))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[25\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (704:704:704))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1161:1161:1161) (1269:1269:1269))
        (PORT asdata (2128:2128:2128) (2390:2390:2390))
        (PORT ena (659:659:659) (712:712:712))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[26\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (153:153:153) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1161:1161:1161) (1269:1269:1269))
        (PORT asdata (1979:1979:1979) (2194:2194:2194))
        (PORT ena (659:659:659) (712:712:712))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (565:565:565) (672:672:672))
        (PORT d[1] (537:537:537) (634:634:634))
        (PORT d[2] (541:541:541) (644:644:644))
        (PORT d[3] (723:723:723) (838:838:838))
        (PORT d[4] (723:723:723) (845:845:845))
        (PORT d[5] (546:546:546) (645:645:645))
        (PORT d[6] (725:725:725) (850:850:850))
        (PORT d[7] (533:533:533) (631:631:631))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (819:819:819) (953:953:953))
        (PORT d[1] (1064:1064:1064) (1240:1240:1240))
        (PORT d[2] (751:751:751) (875:875:875))
        (PORT d[3] (1059:1059:1059) (1218:1218:1218))
        (PORT d[4] (722:722:722) (828:828:828))
        (PORT d[5] (1511:1511:1511) (1746:1746:1746))
        (PORT d[6] (1354:1354:1354) (1557:1557:1557))
        (PORT d[7] (1356:1356:1356) (1569:1569:1569))
        (PORT d[8] (808:808:808) (923:923:923))
        (PORT d[9] (765:765:765) (884:884:884))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (815:815:815) (871:871:871))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (PORT d[0] (1099:1099:1099) (1164:1164:1164))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1002:1002:1002) (1149:1149:1149))
        (PORT d[1] (850:850:850) (977:977:977))
        (PORT d[2] (676:676:676) (777:777:777))
        (PORT d[3] (846:846:846) (983:983:983))
        (PORT d[4] (640:640:640) (731:731:731))
        (PORT d[5] (1232:1232:1232) (1401:1401:1401))
        (PORT d[6] (1503:1503:1503) (1701:1701:1701))
        (PORT d[7] (630:630:630) (714:714:714))
        (PORT d[8] (1337:1337:1337) (1516:1516:1516))
        (PORT d[9] (1175:1175:1175) (1346:1346:1346))
        (PORT clk (1053:1053:1053) (1072:1072:1072))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1072:1072:1072))
        (PORT d[0] (438:438:438) (461:461:461))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1073:1073:1073))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1073:1073:1073))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1073:1073:1073))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (698:698:698) (844:844:844))
        (PORT datab (560:560:560) (679:679:679))
        (PORT datac (450:450:450) (505:505:505))
        (PORT datad (598:598:598) (686:686:686))
        (IOPATH dataa combout (158:158:158) (173:173:173))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (386:386:386) (472:472:472))
        (PORT datac (328:328:328) (390:390:390))
        (PORT datad (316:316:316) (378:378:378))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE LessThan0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (377:377:377) (459:459:459))
        (PORT datab (391:391:391) (469:469:469))
        (PORT datac (360:360:360) (438:438:438))
        (PORT datad (378:378:378) (446:446:446))
        (IOPATH dataa combout (166:166:166) (163:163:163))
        (IOPATH datab combout (167:167:167) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (105:105:105) (137:137:137))
        (PORT datab (109:109:109) (139:139:139))
        (PORT datac (331:331:331) (396:396:396))
        (PORT datad (165:165:165) (193:193:193))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (634:634:634) (747:747:747))
        (PORT datab (103:103:103) (131:131:131))
        (PORT datac (88:88:88) (110:110:110))
        (PORT datad (610:610:610) (699:699:699))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (166:166:166) (158:158:158))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1135:1135:1135) (1316:1316:1316))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1133:1133:1133) (1327:1327:1327))
        (PORT d[1] (1375:1375:1375) (1620:1620:1620))
        (PORT d[2] (1534:1534:1534) (1764:1764:1764))
        (PORT d[3] (917:917:917) (1067:1067:1067))
        (PORT d[4] (963:963:963) (1110:1110:1110))
        (PORT d[5] (836:836:836) (965:965:965))
        (PORT d[6] (1196:1196:1196) (1386:1386:1386))
        (PORT d[7] (1160:1160:1160) (1331:1331:1331))
        (PORT d[8] (817:817:817) (942:942:942))
        (PORT d[9] (1031:1031:1031) (1169:1169:1169))
        (PORT d[10] (848:848:848) (972:972:972))
        (PORT d[11] (1418:1418:1418) (1614:1614:1614))
        (PORT d[12] (1361:1361:1361) (1572:1572:1572))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1231:1231:1231) (1343:1343:1343))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (PORT d[0] (1517:1517:1517) (1639:1639:1639))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1222:1222:1222) (1415:1415:1415))
        (PORT d[1] (931:931:931) (1096:1096:1096))
        (PORT d[2] (1256:1256:1256) (1459:1459:1459))
        (PORT d[3] (1262:1262:1262) (1466:1466:1466))
        (PORT d[4] (1524:1524:1524) (1740:1740:1740))
        (PORT d[5] (1447:1447:1447) (1654:1654:1654))
        (PORT d[6] (1308:1308:1308) (1500:1500:1500))
        (PORT d[7] (719:719:719) (820:820:820))
        (PORT d[8] (1619:1619:1619) (1856:1856:1856))
        (PORT d[9] (1371:1371:1371) (1574:1574:1574))
        (PORT d[10] (1549:1549:1549) (1763:1763:1763))
        (PORT d[11] (1358:1358:1358) (1557:1557:1557))
        (PORT d[12] (676:676:676) (779:779:779))
        (PORT clk (1048:1048:1048) (1067:1067:1067))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1067:1067:1067))
        (PORT d[0] (1142:1142:1142) (1272:1272:1272))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1291:1291:1291) (1485:1485:1485))
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1124:1124:1124) (1331:1331:1331))
        (PORT d[1] (1211:1211:1211) (1436:1436:1436))
        (PORT d[2] (1526:1526:1526) (1755:1755:1755))
        (PORT d[3] (941:941:941) (1099:1099:1099))
        (PORT d[4] (973:973:973) (1129:1129:1129))
        (PORT d[5] (823:823:823) (947:947:947))
        (PORT d[6] (1502:1502:1502) (1743:1743:1743))
        (PORT d[7] (1163:1163:1163) (1336:1336:1336))
        (PORT d[8] (853:853:853) (991:991:991))
        (PORT d[9] (1070:1070:1070) (1223:1223:1223))
        (PORT d[10] (854:854:854) (979:979:979))
        (PORT d[11] (1423:1423:1423) (1625:1625:1625))
        (PORT d[12] (1388:1388:1388) (1607:1607:1607))
        (PORT clk (1088:1088:1088) (1105:1105:1105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1222:1222:1222) (1356:1356:1356))
        (PORT clk (1088:1088:1088) (1105:1105:1105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (PORT d[0] (1506:1506:1506) (1649:1649:1649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1041:1041:1041) (1206:1206:1206))
        (PORT d[1] (1246:1246:1246) (1445:1445:1445))
        (PORT d[2] (1245:1245:1245) (1444:1444:1444))
        (PORT d[3] (1091:1091:1091) (1263:1263:1263))
        (PORT d[4] (1542:1542:1542) (1762:1762:1762))
        (PORT d[5] (1447:1447:1447) (1652:1652:1652))
        (PORT d[6] (1283:1283:1283) (1463:1463:1463))
        (PORT d[7] (1036:1036:1036) (1178:1178:1178))
        (PORT d[8] (1607:1607:1607) (1837:1837:1837))
        (PORT d[9] (1374:1374:1374) (1581:1581:1581))
        (PORT d[10] (1556:1556:1556) (1772:1772:1772))
        (PORT d[11] (1360:1360:1360) (1561:1561:1561))
        (PORT d[12] (682:682:682) (791:791:791))
        (PORT clk (1047:1047:1047) (1066:1066:1066))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1047:1047:1047) (1066:1066:1066))
        (PORT d[0] (577:577:577) (633:633:633))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1067:1067:1067))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1067:1067:1067))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1067:1067:1067))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (691:691:691) (836:836:836))
        (PORT datab (367:367:367) (424:424:424))
        (PORT datac (497:497:497) (572:572:572))
        (PORT datad (545:545:545) (657:657:657))
        (IOPATH dataa combout (188:188:188) (184:184:184))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (832:832:832) (970:970:970))
        (PORT clk (1084:1084:1084) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1301:1301:1301) (1516:1516:1516))
        (PORT d[1] (1325:1325:1325) (1555:1555:1555))
        (PORT d[2] (1341:1341:1341) (1540:1540:1540))
        (PORT d[3] (1092:1092:1092) (1266:1266:1266))
        (PORT d[4] (1132:1132:1132) (1301:1301:1301))
        (PORT d[5] (1038:1038:1038) (1200:1200:1200))
        (PORT d[6] (1332:1332:1332) (1564:1564:1564))
        (PORT d[7] (1145:1145:1145) (1313:1313:1313))
        (PORT d[8] (990:990:990) (1137:1137:1137))
        (PORT d[9] (1092:1092:1092) (1237:1237:1237))
        (PORT d[10] (1034:1034:1034) (1179:1179:1179))
        (PORT d[11] (955:955:955) (1090:1090:1090))
        (PORT d[12] (1205:1205:1205) (1400:1400:1400))
        (PORT clk (1082:1082:1082) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1100:1100:1100) (1225:1225:1225))
        (PORT clk (1082:1082:1082) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1084:1084:1084) (1102:1102:1102))
        (PORT d[0] (1384:1384:1384) (1518:1518:1518))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1009:1009:1009) (1167:1167:1167))
        (PORT d[1] (721:721:721) (852:852:852))
        (PORT d[2] (1161:1161:1161) (1348:1348:1348))
        (PORT d[3] (748:748:748) (884:884:884))
        (PORT d[4] (1702:1702:1702) (1940:1940:1940))
        (PORT d[5] (1790:1790:1790) (2054:2054:2054))
        (PORT d[6] (1486:1486:1486) (1700:1700:1700))
        (PORT d[7] (636:636:636) (728:728:728))
        (PORT d[8] (1803:1803:1803) (2063:2063:2063))
        (PORT d[9] (1566:1566:1566) (1804:1804:1804))
        (PORT d[10] (1724:1724:1724) (1961:1961:1961))
        (PORT d[11] (1521:1521:1521) (1740:1740:1740))
        (PORT d[12] (649:649:649) (750:750:750))
        (PORT clk (1041:1041:1041) (1061:1061:1061))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1041:1041:1041) (1061:1061:1061))
        (PORT d[0] (421:421:421) (455:455:455))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1042:1042:1042) (1062:1062:1062))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1042:1042:1042) (1062:1062:1062))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1042:1042:1042) (1062:1062:1062))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (697:697:697) (843:843:843))
        (PORT datab (560:560:560) (680:680:680))
        (PORT datac (346:346:346) (394:394:394))
        (PORT datad (582:582:582) (661:661:661))
        (IOPATH dataa combout (158:158:158) (173:173:173))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (103:103:103) (134:134:134))
        (PORT datab (104:104:104) (133:133:133))
        (PORT datac (623:623:623) (730:730:730))
        (PORT datad (611:611:611) (700:700:700))
        (IOPATH dataa combout (165:165:165) (159:159:159))
        (IOPATH datab combout (166:166:166) (158:158:158))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (868:868:868) (1013:1013:1013))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1101:1101:1101) (1297:1297:1297))
        (PORT d[1] (1382:1382:1382) (1628:1628:1628))
        (PORT d[2] (1557:1557:1557) (1797:1797:1797))
        (PORT d[3] (741:741:741) (865:865:865))
        (PORT d[4] (797:797:797) (919:919:919))
        (PORT d[5] (668:668:668) (775:775:775))
        (PORT d[6] (1216:1216:1216) (1412:1412:1412))
        (PORT d[7] (796:796:796) (911:911:911))
        (PORT d[8] (668:668:668) (775:775:775))
        (PORT d[9] (1092:1092:1092) (1246:1246:1246))
        (PORT d[10] (681:681:681) (781:781:781))
        (PORT d[11] (1564:1564:1564) (1782:1782:1782))
        (PORT d[12] (642:642:642) (743:743:743))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1225:1225:1225) (1361:1361:1361))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (1509:1509:1509) (1654:1654:1654))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1230:1230:1230) (1423:1423:1423))
        (PORT d[1] (920:920:920) (1083:1083:1083))
        (PORT d[2] (1067:1067:1067) (1242:1242:1242))
        (PORT d[3] (1256:1256:1256) (1464:1464:1464))
        (PORT d[4] (1361:1361:1361) (1556:1556:1556))
        (PORT d[5] (1290:1290:1290) (1476:1476:1476))
        (PORT d[6] (1122:1122:1122) (1285:1285:1285))
        (PORT d[7] (901:901:901) (1032:1032:1032))
        (PORT d[8] (1422:1422:1422) (1623:1623:1623))
        (PORT d[9] (1181:1181:1181) (1357:1357:1357))
        (PORT d[10] (1427:1427:1427) (1634:1634:1634))
        (PORT d[11] (1165:1165:1165) (1336:1336:1336))
        (PORT d[12] (1316:1316:1316) (1505:1505:1505))
        (PORT clk (1049:1049:1049) (1069:1069:1069))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1069:1069:1069))
        (PORT d[0] (742:742:742) (816:816:816))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1036:1036:1036) (1201:1201:1201))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1118:1118:1118) (1319:1319:1319))
        (PORT d[1] (1370:1370:1370) (1612:1612:1612))
        (PORT d[2] (1534:1534:1534) (1765:1765:1765))
        (PORT d[3] (875:875:875) (1018:1018:1018))
        (PORT d[4] (810:810:810) (941:941:941))
        (PORT d[5] (656:656:656) (755:755:755))
        (PORT d[6] (1215:1215:1215) (1411:1411:1411))
        (PORT d[7] (1161:1161:1161) (1332:1332:1332))
        (PORT d[8] (655:655:655) (755:755:755))
        (PORT d[9] (1077:1077:1077) (1232:1232:1232))
        (PORT d[10] (682:682:682) (782:782:782))
        (PORT d[11] (1432:1432:1432) (1635:1635:1635))
        (PORT d[12] (874:874:874) (1014:1014:1014))
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1248:1248:1248) (1365:1365:1365))
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (PORT d[0] (1532:1532:1532) (1658:1658:1658))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1230:1230:1230) (1425:1425:1425))
        (PORT d[1] (935:935:935) (1092:1092:1092))
        (PORT d[2] (1247:1247:1247) (1449:1449:1449))
        (PORT d[3] (1278:1278:1278) (1489:1489:1489))
        (PORT d[4] (1182:1182:1182) (1348:1348:1348))
        (PORT d[5] (1291:1291:1291) (1477:1477:1477))
        (PORT d[6] (1282:1282:1282) (1466:1466:1466))
        (PORT d[7] (658:658:658) (756:756:756))
        (PORT d[8] (1598:1598:1598) (1827:1827:1827))
        (PORT d[9] (1353:1353:1353) (1552:1552:1552))
        (PORT d[10] (1549:1549:1549) (1768:1768:1768))
        (PORT d[11] (1339:1339:1339) (1536:1536:1536))
        (PORT d[12] (1324:1324:1324) (1516:1516:1516))
        (PORT clk (1049:1049:1049) (1068:1068:1068))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (PORT d[0] (965:965:965) (1076:1076:1076))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1069:1069:1069))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1069:1069:1069))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1069:1069:1069))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (377:377:377) (438:438:438))
        (PORT datab (561:561:561) (681:681:681))
        (PORT datac (447:447:447) (503:503:503))
        (PORT datad (681:681:681) (812:812:812))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (552:552:552) (650:650:650))
        (PORT clk (1087:1087:1087) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1002:1002:1002) (1162:1162:1162))
        (PORT d[1] (1071:1071:1071) (1255:1255:1255))
        (PORT d[2] (920:920:920) (1062:1062:1062))
        (PORT d[3] (943:943:943) (1090:1090:1090))
        (PORT d[4] (886:886:886) (1012:1012:1012))
        (PORT d[5] (1402:1402:1402) (1620:1620:1620))
        (PORT d[6] (1493:1493:1493) (1738:1738:1738))
        (PORT d[7] (1443:1443:1443) (1666:1666:1666))
        (PORT d[8] (1106:1106:1106) (1257:1257:1257))
        (PORT d[9] (1121:1121:1121) (1294:1294:1294))
        (PORT d[10] (879:879:879) (998:998:998))
        (PORT d[11] (989:989:989) (1124:1124:1124))
        (PORT d[12] (1525:1525:1525) (1762:1762:1762))
        (PORT clk (1085:1085:1085) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1052:1052:1052) (1148:1148:1148))
        (PORT clk (1085:1085:1085) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1106:1106:1106))
        (PORT d[0] (1336:1336:1336) (1441:1441:1441))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (837:837:837) (962:962:962))
        (PORT d[1] (854:854:854) (987:987:987))
        (PORT d[2] (873:873:873) (1012:1012:1012))
        (PORT d[3] (852:852:852) (981:981:981))
        (PORT d[4] (481:481:481) (550:550:550))
        (PORT d[5] (1543:1543:1543) (1742:1742:1742))
        (PORT d[6] (1679:1679:1679) (1899:1899:1899))
        (PORT d[7] (659:659:659) (749:749:749))
        (PORT d[8] (639:639:639) (726:726:726))
        (PORT d[9] (1341:1341:1341) (1529:1529:1529))
        (PORT d[10] (982:982:982) (1119:1119:1119))
        (PORT d[11] (1663:1663:1663) (1880:1880:1880))
        (PORT d[12] (1348:1348:1348) (1532:1532:1532))
        (PORT clk (1044:1044:1044) (1065:1065:1065))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1044:1044:1044) (1065:1065:1065))
        (PORT d[0] (694:694:694) (755:755:755))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1045:1045:1045) (1066:1066:1066))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1045:1045:1045) (1066:1066:1066))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1045:1045:1045) (1066:1066:1066))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (697:697:697) (843:843:843))
        (PORT datab (561:561:561) (680:680:680))
        (PORT datac (757:757:757) (872:872:872))
        (PORT datad (583:583:583) (667:667:667))
        (IOPATH dataa combout (158:158:158) (173:173:173))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (640:640:640) (754:754:754))
        (PORT datab (103:103:103) (132:132:132))
        (PORT datac (90:90:90) (112:112:112))
        (PORT datad (611:611:611) (700:700:700))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (166:166:166) (158:158:158))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (546:546:546) (642:642:642))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1264:1264:1264) (1453:1453:1453))
        (PORT d[1] (964:964:964) (1136:1136:1136))
        (PORT d[2] (1065:1065:1065) (1227:1227:1227))
        (PORT d[3] (943:943:943) (1093:1093:1093))
        (PORT d[4] (889:889:889) (1018:1018:1018))
        (PORT d[5] (1379:1379:1379) (1591:1591:1591))
        (PORT d[6] (1790:1790:1790) (2072:2072:2072))
        (PORT d[7] (1420:1420:1420) (1637:1637:1637))
        (PORT d[8] (965:965:965) (1095:1095:1095))
        (PORT d[9] (949:949:949) (1097:1097:1097))
        (PORT d[10] (874:874:874) (992:992:992))
        (PORT d[11] (872:872:872) (998:998:998))
        (PORT d[12] (1672:1672:1672) (1928:1928:1928))
        (PORT clk (1088:1088:1088) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1024:1024:1024) (1114:1114:1114))
        (PORT clk (1088:1088:1088) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (PORT d[0] (1311:1311:1311) (1406:1406:1406))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (982:982:982) (1126:1126:1126))
        (PORT d[1] (685:685:685) (787:787:787))
        (PORT d[2] (707:707:707) (822:822:822))
        (PORT d[3] (900:900:900) (1075:1075:1075))
        (PORT d[4] (1521:1521:1521) (1733:1733:1733))
        (PORT d[5] (1284:1284:1284) (1451:1451:1451))
        (PORT d[6] (1529:1529:1529) (1734:1734:1734))
        (PORT d[7] (789:789:789) (899:899:899))
        (PORT d[8] (614:614:614) (689:689:689))
        (PORT d[9] (1193:1193:1193) (1366:1366:1366))
        (PORT d[10] (827:827:827) (946:946:946))
        (PORT d[11] (1662:1662:1662) (1879:1879:1879))
        (PORT d[12] (1643:1643:1643) (1866:1866:1866))
        (PORT clk (1047:1047:1047) (1067:1067:1067))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1047:1047:1047) (1067:1067:1067))
        (PORT d[0] (410:410:410) (440:440:440))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (693:693:693) (838:838:838))
        (PORT datab (564:564:564) (683:683:683))
        (PORT datac (753:753:753) (860:860:860))
        (PORT datad (597:597:597) (688:688:688))
        (IOPATH dataa combout (158:158:158) (173:173:173))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (541:541:541) (639:639:639))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1263:1263:1263) (1451:1451:1451))
        (PORT d[1] (934:934:934) (1093:1093:1093))
        (PORT d[2] (1076:1076:1076) (1239:1239:1239))
        (PORT d[3] (785:785:785) (919:919:919))
        (PORT d[4] (879:879:879) (1006:1006:1006))
        (PORT d[5] (1384:1384:1384) (1608:1608:1608))
        (PORT d[6] (1208:1208:1208) (1398:1398:1398))
        (PORT d[7] (1334:1334:1334) (1551:1551:1551))
        (PORT d[8] (970:970:970) (1102:1102:1102))
        (PORT d[9] (942:942:942) (1089:1089:1089))
        (PORT d[10] (1204:1204:1204) (1370:1370:1370))
        (PORT d[11] (858:858:858) (981:981:981))
        (PORT d[12] (1497:1497:1497) (1729:1729:1729))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (961:961:961) (1030:1030:1030))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (1245:1245:1245) (1323:1323:1323))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (995:995:995) (1140:1140:1140))
        (PORT d[1] (811:811:811) (938:938:938))
        (PORT d[2] (706:706:706) (821:821:821))
        (PORT d[3] (547:547:547) (646:646:646))
        (PORT d[4] (1531:1531:1531) (1748:1748:1748))
        (PORT d[5] (1283:1283:1283) (1450:1450:1450))
        (PORT d[6] (1515:1515:1515) (1713:1713:1713))
        (PORT d[7] (475:475:475) (540:540:540))
        (PORT d[8] (835:835:835) (948:948:948))
        (PORT d[9] (1343:1343:1343) (1538:1538:1538))
        (PORT d[10] (813:813:813) (926:926:926))
        (PORT d[11] (1403:1403:1403) (1589:1589:1589))
        (PORT d[12] (1344:1344:1344) (1532:1532:1532))
        (PORT clk (1049:1049:1049) (1069:1069:1069))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1069:1069:1069))
        (PORT d[0] (294:294:294) (307:307:307))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1050:1050:1050) (1070:1070:1070))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (722:722:722) (847:847:847))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (817:817:817) (951:951:951))
        (PORT d[1] (923:923:923) (1080:1080:1080))
        (PORT d[2] (1083:1083:1083) (1246:1246:1246))
        (PORT d[3] (910:910:910) (1053:1053:1053))
        (PORT d[4] (1018:1018:1018) (1161:1161:1161))
        (PORT d[5] (1654:1654:1654) (1914:1914:1914))
        (PORT d[6] (2115:2115:2115) (2438:2438:2438))
        (PORT d[7] (1355:1355:1355) (1572:1572:1572))
        (PORT d[8] (813:813:813) (930:930:930))
        (PORT d[9] (766:766:766) (885:885:885))
        (PORT d[10] (1054:1054:1054) (1194:1194:1194))
        (PORT d[11] (1043:1043:1043) (1191:1191:1191))
        (PORT d[12] (1332:1332:1332) (1545:1545:1545))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (843:843:843) (903:903:903))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (PORT d[0] (1127:1127:1127) (1196:1196:1196))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1175:1175:1175) (1345:1345:1345))
        (PORT d[1] (826:826:826) (954:954:954))
        (PORT d[2] (629:629:629) (723:723:723))
        (PORT d[3] (520:520:520) (609:609:609))
        (PORT d[4] (1513:1513:1513) (1726:1726:1726))
        (PORT d[5] (1287:1287:1287) (1457:1457:1457))
        (PORT d[6] (1507:1507:1507) (1704:1704:1704))
        (PORT d[7] (1192:1192:1192) (1356:1356:1356))
        (PORT d[8] (831:831:831) (942:942:942))
        (PORT d[9] (1186:1186:1186) (1358:1358:1358))
        (PORT d[10] (818:818:818) (937:937:937))
        (PORT d[11] (1493:1493:1493) (1692:1692:1692))
        (PORT d[12] (1186:1186:1186) (1357:1357:1357))
        (PORT clk (1051:1051:1051) (1070:1070:1070))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1070:1070:1070))
        (PORT d[0] (435:435:435) (465:465:465))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1052:1052:1052) (1071:1071:1071))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1052:1052:1052) (1071:1071:1071))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1052:1052:1052) (1071:1071:1071))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (690:690:690) (835:835:835))
        (PORT datab (566:566:566) (686:686:686))
        (PORT datac (747:747:747) (857:857:857))
        (PORT datad (764:764:764) (864:864:864))
        (IOPATH dataa combout (165:165:165) (159:159:159))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (105:105:105) (137:137:137))
        (PORT datab (106:106:106) (135:135:135))
        (PORT datac (617:617:617) (724:724:724))
        (PORT datad (610:610:610) (699:699:699))
        (IOPATH dataa combout (165:165:165) (159:159:159))
        (IOPATH datab combout (166:166:166) (158:158:158))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1176:1176:1176) (1350:1350:1350))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1278:1278:1278) (1498:1498:1498))
        (PORT d[1] (1199:1199:1199) (1419:1419:1419))
        (PORT d[2] (1350:1350:1350) (1553:1553:1553))
        (PORT d[3] (927:927:927) (1078:1078:1078))
        (PORT d[4] (979:979:979) (1129:1129:1129))
        (PORT d[5] (1015:1015:1015) (1173:1173:1173))
        (PORT d[6] (1027:1027:1027) (1198:1198:1198))
        (PORT d[7] (968:968:968) (1106:1106:1106))
        (PORT d[8] (850:850:850) (985:985:985))
        (PORT d[9] (1081:1081:1081) (1235:1235:1235))
        (PORT d[10] (1016:1016:1016) (1160:1160:1160))
        (PORT d[11] (1395:1395:1395) (1588:1588:1588))
        (PORT d[12] (1374:1374:1374) (1587:1587:1587))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1080:1080:1080) (1176:1176:1176))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (PORT d[0] (1364:1364:1364) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1051:1051:1051) (1221:1221:1221))
        (PORT d[1] (1253:1253:1253) (1453:1453:1453))
        (PORT d[2] (1166:1166:1166) (1352:1352:1352))
        (PORT d[3] (920:920:920) (1076:1076:1076))
        (PORT d[4] (1544:1544:1544) (1765:1765:1765))
        (PORT d[5] (1485:1485:1485) (1708:1708:1708))
        (PORT d[6] (1452:1452:1452) (1667:1667:1667))
        (PORT d[7] (816:816:816) (933:933:933))
        (PORT d[8] (1780:1780:1780) (2035:2035:2035))
        (PORT d[9] (1568:1568:1568) (1808:1808:1808))
        (PORT d[10] (1880:1880:1880) (2146:2146:2146))
        (PORT d[11] (1351:1351:1351) (1548:1548:1548))
        (PORT d[12] (659:659:659) (763:763:763))
        (PORT clk (1046:1046:1046) (1065:1065:1065))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1046:1046:1046) (1065:1065:1065))
        (PORT d[0] (1144:1144:1144) (1281:1281:1281))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1047:1047:1047) (1066:1066:1066))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1047:1047:1047) (1066:1066:1066))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1047:1047:1047) (1066:1066:1066))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1013:1013:1013) (1170:1170:1170))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1489:1489:1489) (1744:1744:1744))
        (PORT d[1] (1181:1181:1181) (1396:1396:1396))
        (PORT d[2] (1347:1347:1347) (1550:1550:1550))
        (PORT d[3] (1092:1092:1092) (1264:1264:1264))
        (PORT d[4] (992:992:992) (1152:1152:1152))
        (PORT d[5] (1031:1031:1031) (1192:1192:1192))
        (PORT d[6] (1519:1519:1519) (1768:1768:1768))
        (PORT d[7] (1100:1100:1100) (1258:1258:1258))
        (PORT d[8] (989:989:989) (1136:1136:1136))
        (PORT d[9] (1100:1100:1100) (1257:1257:1257))
        (PORT d[10] (1028:1028:1028) (1172:1172:1172))
        (PORT d[11] (1241:1241:1241) (1411:1411:1411))
        (PORT d[12] (1390:1390:1390) (1612:1612:1612))
        (PORT clk (1085:1085:1085) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1248:1248:1248) (1385:1385:1385))
        (PORT clk (1085:1085:1085) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1104:1104:1104))
        (PORT d[0] (1532:1532:1532) (1678:1678:1678))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1044:1044:1044) (1213:1213:1213))
        (PORT d[1] (1098:1098:1098) (1283:1283:1283))
        (PORT d[2] (1170:1170:1170) (1358:1358:1358))
        (PORT d[3] (919:919:919) (1077:1077:1077))
        (PORT d[4] (1712:1712:1712) (1957:1957:1957))
        (PORT d[5] (1642:1642:1642) (1886:1886:1886))
        (PORT d[6] (1462:1462:1462) (1670:1670:1670))
        (PORT d[7] (530:530:530) (614:614:614))
        (PORT d[8] (1783:1783:1783) (2036:2036:2036))
        (PORT d[9] (1566:1566:1566) (1803:1803:1803))
        (PORT d[10] (1726:1726:1726) (1967:1967:1967))
        (PORT d[11] (1519:1519:1519) (1742:1742:1742))
        (PORT d[12] (517:517:517) (601:601:601))
        (PORT clk (1044:1044:1044) (1063:1063:1063))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1044:1044:1044) (1063:1063:1063))
        (PORT d[0] (737:737:737) (809:809:809))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1045:1045:1045) (1064:1064:1064))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1045:1045:1045) (1064:1064:1064))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1045:1045:1045) (1064:1064:1064))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (474:474:474) (545:545:545))
        (PORT datab (566:566:566) (687:687:687))
        (PORT datac (343:343:343) (390:390:390))
        (PORT datad (674:674:674) (804:804:804))
        (IOPATH dataa combout (166:166:166) (159:159:159))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (862:862:862) (1003:1003:1003))
        (PORT clk (1082:1082:1082) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1305:1305:1305) (1534:1534:1534))
        (PORT d[1] (1138:1138:1138) (1352:1352:1352))
        (PORT d[2] (1041:1041:1041) (1202:1202:1202))
        (PORT d[3] (1114:1114:1114) (1292:1292:1292))
        (PORT d[4] (1143:1143:1143) (1318:1318:1318))
        (PORT d[5] (1026:1026:1026) (1180:1180:1180))
        (PORT d[6] (1341:1341:1341) (1566:1566:1566))
        (PORT d[7] (1140:1140:1140) (1306:1306:1306))
        (PORT d[8] (1011:1011:1011) (1165:1165:1165))
        (PORT d[9] (1113:1113:1113) (1269:1269:1269))
        (PORT d[10] (1035:1035:1035) (1180:1180:1180))
        (PORT d[11] (949:949:949) (1082:1082:1082))
        (PORT d[12] (1203:1203:1203) (1397:1397:1397))
        (PORT clk (1080:1080:1080) (1098:1098:1098))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1120:1120:1120) (1247:1247:1247))
        (PORT clk (1080:1080:1080) (1098:1098:1098))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1082:1082:1082) (1100:1100:1100))
        (PORT d[0] (1404:1404:1404) (1540:1540:1540))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (841:841:841) (976:976:976))
        (PORT d[1] (856:856:856) (995:995:995))
        (PORT d[2] (879:879:879) (1029:1029:1029))
        (PORT d[3] (865:865:865) (1005:1005:1005))
        (PORT d[4] (1718:1718:1718) (1960:1960:1960))
        (PORT d[5] (1656:1656:1656) (1901:1901:1901))
        (PORT d[6] (1492:1492:1492) (1706:1706:1706))
        (PORT d[7] (660:660:660) (764:764:764))
        (PORT d[8] (1791:1791:1791) (2044:2044:2044))
        (PORT d[9] (1717:1717:1717) (1970:1970:1970))
        (PORT d[10] (1730:1730:1730) (1967:1967:1967))
        (PORT d[11] (1537:1537:1537) (1760:1760:1760))
        (PORT d[12] (649:649:649) (748:748:748))
        (PORT clk (1039:1039:1039) (1059:1059:1059))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1039:1039:1039) (1059:1059:1059))
        (PORT d[0] (587:587:587) (645:645:645))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1040:1040:1040) (1060:1060:1060))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1040:1040:1040) (1060:1060:1060))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1040:1040:1040) (1060:1060:1060))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (696:696:696) (841:841:841))
        (PORT datab (562:562:562) (681:681:681))
        (PORT datac (450:450:450) (513:513:513))
        (PORT datad (583:583:583) (664:664:664))
        (IOPATH dataa combout (158:158:158) (173:173:173))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (195:195:195) (233:233:233))
        (PORT datab (104:104:104) (132:132:132))
        (PORT datac (625:625:625) (732:732:732))
        (PORT datad (611:611:611) (700:700:700))
        (IOPATH dataa combout (165:165:165) (159:159:159))
        (IOPATH datab combout (166:166:166) (158:158:158))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (704:704:704) (826:826:826))
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1296:1296:1296) (1508:1508:1508))
        (PORT d[1] (582:582:582) (684:684:684))
        (PORT d[2] (926:926:926) (1074:1074:1074))
        (PORT d[3] (591:591:591) (695:695:695))
        (PORT d[4] (564:564:564) (658:658:658))
        (PORT d[5] (553:553:553) (632:632:632))
        (PORT d[6] (1529:1529:1529) (1753:1753:1753))
        (PORT d[7] (1573:1573:1573) (1825:1825:1825))
        (PORT d[8] (1289:1289:1289) (1466:1466:1466))
        (PORT d[9] (581:581:581) (675:675:675))
        (PORT d[10] (1244:1244:1244) (1411:1411:1411))
        (PORT d[11] (891:891:891) (1023:1023:1023))
        (PORT d[12] (528:528:528) (605:605:605))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (681:681:681) (721:721:721))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (PORT d[0] (965:965:965) (1014:1014:1014))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (876:876:876) (1013:1013:1013))
        (PORT d[1] (1166:1166:1166) (1324:1324:1324))
        (PORT d[2] (739:739:739) (855:855:855))
        (PORT d[3] (550:550:550) (657:657:657))
        (PORT d[4] (1339:1339:1339) (1528:1528:1528))
        (PORT d[5] (959:959:959) (1092:1092:1092))
        (PORT d[6] (1158:1158:1158) (1313:1313:1313))
        (PORT d[7] (1000:1000:1000) (1137:1137:1137))
        (PORT d[8] (1171:1171:1171) (1328:1328:1328))
        (PORT d[9] (995:995:995) (1139:1139:1139))
        (PORT d[10] (964:964:964) (1103:1103:1103))
        (PORT d[11] (1309:1309:1309) (1484:1484:1484))
        (PORT d[12] (1157:1157:1157) (1318:1318:1318))
        (PORT clk (1055:1055:1055) (1074:1074:1074))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (PORT d[0] (606:606:606) (667:667:667))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1056:1056:1056) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1056:1056:1056) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1056:1056:1056) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (565:565:565) (677:677:677))
        (PORT datab (639:639:639) (744:744:744))
        (PORT datac (562:562:562) (679:679:679))
        (PORT datad (468:468:468) (537:537:537))
        (IOPATH dataa combout (172:172:172) (163:163:163))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (719:719:719) (838:838:838))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1305:1305:1305) (1518:1518:1518))
        (PORT d[1] (771:771:771) (904:904:904))
        (PORT d[2] (713:713:713) (827:827:827))
        (PORT d[3] (414:414:414) (488:488:488))
        (PORT d[4] (385:385:385) (447:447:447))
        (PORT d[5] (372:372:372) (430:430:430))
        (PORT d[6] (373:373:373) (429:429:429))
        (PORT d[7] (378:378:378) (435:435:435))
        (PORT d[8] (361:361:361) (413:413:413))
        (PORT d[9] (921:921:921) (1067:1067:1067))
        (PORT d[10] (393:393:393) (450:450:450))
        (PORT d[11] (1050:1050:1050) (1204:1204:1204))
        (PORT d[12] (379:379:379) (439:439:439))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (511:511:511) (523:523:523))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (795:795:795) (816:816:816))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1016:1016:1016) (1164:1164:1164))
        (PORT d[1] (1001:1001:1001) (1152:1152:1152))
        (PORT d[2] (890:890:890) (1031:1031:1031))
        (PORT d[3] (717:717:717) (843:843:843))
        (PORT d[4] (1156:1156:1156) (1318:1318:1318))
        (PORT d[5] (1110:1110:1110) (1267:1267:1267))
        (PORT d[6] (804:804:804) (909:909:909))
        (PORT d[7] (981:981:981) (1112:1112:1112))
        (PORT d[8] (1143:1143:1143) (1297:1297:1297))
        (PORT d[9] (1150:1150:1150) (1307:1307:1307))
        (PORT d[10] (1004:1004:1004) (1152:1152:1152))
        (PORT d[11] (1080:1080:1080) (1221:1221:1221))
        (PORT d[12] (818:818:818) (934:934:934))
        (PORT clk (1054:1054:1054) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1073:1073:1073))
        (PORT d[0] (630:630:630) (688:688:688))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (877:877:877) (1019:1019:1019))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1304:1304:1304) (1511:1511:1511))
        (PORT d[1] (556:556:556) (640:640:640))
        (PORT d[2] (568:568:568) (667:667:667))
        (PORT d[3] (725:725:725) (839:839:839))
        (PORT d[4] (556:556:556) (641:641:641))
        (PORT d[5] (543:543:543) (621:621:621))
        (PORT d[6] (552:552:552) (630:630:630))
        (PORT d[7] (1740:1740:1740) (2011:2011:2011))
        (PORT d[8] (1474:1474:1474) (1678:1678:1678))
        (PORT d[9] (570:570:570) (658:658:658))
        (PORT d[10] (556:556:556) (636:636:636))
        (PORT d[11] (1080:1080:1080) (1240:1240:1240))
        (PORT d[12] (562:562:562) (645:645:645))
        (PORT clk (1093:1093:1093) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (815:815:815) (866:866:866))
        (PORT clk (1093:1093:1093) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (PORT d[0] (1099:1099:1099) (1159:1159:1159))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (881:881:881) (1016:1016:1016))
        (PORT d[1] (699:699:699) (808:808:808))
        (PORT d[2] (909:909:909) (1052:1052:1052))
        (PORT d[3] (706:706:706) (826:826:826))
        (PORT d[4] (991:991:991) (1124:1124:1124))
        (PORT d[5] (1001:1001:1001) (1139:1139:1139))
        (PORT d[6] (956:956:956) (1077:1077:1077))
        (PORT d[7] (1011:1011:1011) (1149:1149:1149))
        (PORT d[8] (1135:1135:1135) (1282:1282:1282))
        (PORT d[9] (977:977:977) (1108:1108:1108))
        (PORT d[10] (983:983:983) (1119:1119:1119))
        (PORT d[11] (955:955:955) (1079:1079:1079))
        (PORT d[12] (983:983:983) (1117:1117:1117))
        (PORT clk (1052:1052:1052) (1071:1071:1071))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1052:1052:1052) (1071:1071:1071))
        (PORT d[0] (982:982:982) (1085:1085:1085))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1072:1072:1072))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1072:1072:1072))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1072:1072:1072))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT dataa (571:571:571) (684:684:684))
        (PORT datab (640:640:640) (737:737:737))
        (PORT datac (569:569:569) (688:688:688))
        (PORT datad (790:790:790) (904:904:904))
        (IOPATH dataa combout (170:170:170) (165:165:165))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (120:120:120) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (510:510:510) (599:599:599))
        (PORT datab (415:415:415) (511:511:511))
        (PORT datac (90:90:90) (112:112:112))
        (PORT datad (91:91:91) (109:109:109))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (550:550:550) (649:649:649))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (637:637:637) (743:743:743))
        (PORT d[1] (1092:1092:1092) (1274:1274:1274))
        (PORT d[2] (919:919:919) (1065:1065:1065))
        (PORT d[3] (747:747:747) (868:868:868))
        (PORT d[4] (713:713:713) (819:819:819))
        (PORT d[5] (573:573:573) (658:658:658))
        (PORT d[6] (1375:1375:1375) (1585:1585:1585))
        (PORT d[7] (1365:1365:1365) (1579:1579:1579))
        (PORT d[8] (1097:1097:1097) (1245:1245:1245))
        (PORT d[9] (576:576:576) (664:664:664))
        (PORT d[10] (1237:1237:1237) (1403:1403:1403))
        (PORT d[11] (879:879:879) (1011:1011:1011))
        (PORT d[12] (1526:1526:1526) (1767:1767:1767))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (796:796:796) (847:847:847))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (1080:1080:1080) (1140:1140:1140))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (893:893:893) (1031:1031:1031))
        (PORT d[1] (1011:1011:1011) (1165:1165:1165))
        (PORT d[2] (698:698:698) (814:814:814))
        (PORT d[3] (683:683:683) (790:790:790))
        (PORT d[4] (1349:1349:1349) (1539:1539:1539))
        (PORT d[5] (1073:1073:1073) (1213:1213:1213))
        (PORT d[6] (1330:1330:1330) (1508:1508:1508))
        (PORT d[7] (1033:1033:1033) (1179:1179:1179))
        (PORT d[8] (1014:1014:1014) (1155:1155:1155))
        (PORT d[9] (1016:1016:1016) (1164:1164:1164))
        (PORT d[10] (825:825:825) (952:952:952))
        (PORT d[11] (1239:1239:1239) (1408:1408:1408))
        (PORT d[12] (1013:1013:1013) (1160:1160:1160))
        (PORT clk (1054:1054:1054) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1073:1073:1073))
        (PORT d[0] (612:612:612) (675:675:675))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (574:574:574) (683:683:683))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (984:984:984) (1139:1139:1139))
        (PORT d[1] (1076:1076:1076) (1253:1253:1253))
        (PORT d[2] (906:906:906) (1052:1052:1052))
        (PORT d[3] (766:766:766) (898:898:898))
        (PORT d[4] (1024:1024:1024) (1168:1168:1168))
        (PORT d[5] (1506:1506:1506) (1739:1739:1739))
        (PORT d[6] (1361:1361:1361) (1565:1565:1565))
        (PORT d[7] (1377:1377:1377) (1598:1598:1598))
        (PORT d[8] (1098:1098:1098) (1249:1249:1249))
        (PORT d[9] (770:770:770) (895:895:895))
        (PORT d[10] (715:715:715) (814:814:814))
        (PORT d[11] (702:702:702) (808:808:808))
        (PORT d[12] (1515:1515:1515) (1753:1753:1753))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (813:813:813) (867:867:867))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (1097:1097:1097) (1160:1160:1160))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (512:512:512) (586:586:586))
        (PORT d[1] (835:835:835) (965:965:965))
        (PORT d[2] (553:553:553) (646:646:646))
        (PORT d[3] (360:360:360) (423:423:423))
        (PORT d[4] (1336:1336:1336) (1522:1522:1522))
        (PORT d[5] (1080:1080:1080) (1224:1224:1224))
        (PORT d[6] (1324:1324:1324) (1496:1496:1496))
        (PORT d[7] (1034:1034:1034) (1180:1180:1180))
        (PORT d[8] (1015:1015:1015) (1155:1155:1155))
        (PORT d[9] (1017:1017:1017) (1165:1165:1165))
        (PORT d[10] (923:923:923) (1052:1052:1052))
        (PORT d[11] (1473:1473:1473) (1665:1665:1665))
        (PORT d[12] (1337:1337:1337) (1532:1532:1532))
        (PORT clk (1054:1054:1054) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1073:1073:1073))
        (PORT d[0] (574:574:574) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT dataa (590:590:590) (709:709:709))
        (PORT datab (622:622:622) (714:714:714))
        (PORT datac (553:553:553) (658:658:658))
        (PORT datad (638:638:638) (730:730:730))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (564:564:564) (667:667:667))
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1122:1122:1122) (1307:1307:1307))
        (PORT d[1] (587:587:587) (690:690:690))
        (PORT d[2] (926:926:926) (1073:1073:1073))
        (PORT d[3] (854:854:854) (984:984:984))
        (PORT d[4] (560:560:560) (648:648:648))
        (PORT d[5] (658:658:658) (749:749:749))
        (PORT d[6] (902:902:902) (1043:1043:1043))
        (PORT d[7] (1578:1578:1578) (1836:1836:1836))
        (PORT d[8] (642:642:642) (737:737:737))
        (PORT d[9] (575:575:575) (663:663:663))
        (PORT d[10] (1231:1231:1231) (1391:1391:1391))
        (PORT d[11] (894:894:894) (1029:1029:1029))
        (PORT d[12] (1513:1513:1513) (1749:1749:1749))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (696:696:696) (744:744:744))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (PORT d[0] (980:980:980) (1037:1037:1037))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (876:876:876) (1011:1011:1011))
        (PORT d[1] (1004:1004:1004) (1151:1151:1151))
        (PORT d[2] (721:721:721) (830:830:830))
        (PORT d[3] (676:676:676) (794:794:794))
        (PORT d[4] (1358:1358:1358) (1551:1551:1551))
        (PORT d[5] (1063:1063:1063) (1204:1204:1204))
        (PORT d[6] (1318:1318:1318) (1490:1490:1490))
        (PORT d[7] (1026:1026:1026) (1171:1171:1171))
        (PORT d[8] (1171:1171:1171) (1329:1329:1329))
        (PORT d[9] (1008:1008:1008) (1154:1154:1154))
        (PORT d[10] (963:963:963) (1103:1103:1103))
        (PORT d[11] (1316:1316:1316) (1491:1491:1491))
        (PORT d[12] (999:999:999) (1139:1139:1139))
        (PORT clk (1055:1055:1055) (1074:1074:1074))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (PORT d[0] (566:566:566) (616:616:616))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1056:1056:1056) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1056:1056:1056) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1056:1056:1056) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT dataa (570:570:570) (682:682:682))
        (PORT datab (644:644:644) (746:746:746))
        (PORT datac (568:568:568) (686:686:686))
        (PORT datad (602:602:602) (689:689:689))
        (IOPATH dataa combout (172:172:172) (163:163:163))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT dataa (509:509:509) (599:599:599))
        (PORT datab (415:415:415) (511:511:511))
        (PORT datac (89:89:89) (110:110:110))
        (PORT datad (90:90:90) (107:107:107))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (104:104:104) (136:136:136))
        (PORT datab (412:412:412) (508:508:508))
        (PORT datac (603:603:603) (710:710:710))
        (PORT datad (389:389:389) (463:463:463))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (755:755:755) (898:898:898))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1133:1133:1133) (1319:1319:1319))
        (PORT d[1] (763:763:763) (896:896:896))
        (PORT d[2] (738:738:738) (858:858:858))
        (PORT d[3] (583:583:583) (686:686:686))
        (PORT d[4] (535:535:535) (620:620:620))
        (PORT d[5] (549:549:549) (632:632:632))
        (PORT d[6] (1538:1538:1538) (1763:1763:1763))
        (PORT d[7] (1568:1568:1568) (1816:1816:1816))
        (PORT d[8] (1283:1283:1283) (1457:1457:1457))
        (PORT d[9] (546:546:546) (629:629:629))
        (PORT d[10] (542:542:542) (621:621:621))
        (PORT d[11] (908:908:908) (1048:1048:1048))
        (PORT d[12] (1703:1703:1703) (1965:1965:1965))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (526:526:526) (540:540:540))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (810:810:810) (833:833:833))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (721:721:721) (827:827:827))
        (PORT d[1] (1004:1004:1004) (1153:1153:1153))
        (PORT d[2] (727:727:727) (847:847:847))
        (PORT d[3] (547:547:547) (647:647:647))
        (PORT d[4] (1146:1146:1146) (1304:1304:1304))
        (PORT d[5] (818:818:818) (933:933:933))
        (PORT d[6] (1141:1141:1141) (1287:1287:1287))
        (PORT d[7] (823:823:823) (938:938:938))
        (PORT d[8] (814:814:814) (925:925:925))
        (PORT d[9] (832:832:832) (952:952:952))
        (PORT d[10] (816:816:816) (931:931:931))
        (PORT d[11] (929:929:929) (1057:1057:1057))
        (PORT d[12] (986:986:986) (1128:1128:1128))
        (PORT clk (1054:1054:1054) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1073:1073:1073))
        (PORT d[0] (737:737:737) (813:813:813))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (586:586:586) (704:704:704))
        (PORT datab (643:643:643) (744:744:744))
        (PORT datac (549:549:549) (654:654:654))
        (PORT datad (615:615:615) (702:702:702))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (993:993:993) (1175:1175:1175))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1252:1252:1252) (1465:1465:1465))
        (PORT d[1] (1556:1556:1556) (1822:1822:1822))
        (PORT d[2] (1732:1732:1732) (1993:1993:1993))
        (PORT d[3] (561:561:561) (661:661:661))
        (PORT d[4] (611:611:611) (697:697:697))
        (PORT d[5] (467:467:467) (542:542:542))
        (PORT d[6] (936:936:936) (1091:1091:1091))
        (PORT d[7] (453:453:453) (523:523:523))
        (PORT d[8] (474:474:474) (550:550:550))
        (PORT d[9] (452:452:452) (520:520:520))
        (PORT d[10] (495:495:495) (572:572:572))
        (PORT d[11] (1628:1628:1628) (1860:1860:1860))
        (PORT d[12] (1103:1103:1103) (1266:1266:1266))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1433:1433:1433) (1573:1573:1573))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (PORT d[0] (1717:1717:1717) (1866:1866:1866))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1005:1005:1005) (1151:1151:1151))
        (PORT d[1] (882:882:882) (1030:1030:1030))
        (PORT d[2] (1048:1048:1048) (1222:1222:1222))
        (PORT d[3] (1071:1071:1071) (1255:1255:1255))
        (PORT d[4] (995:995:995) (1137:1137:1137))
        (PORT d[5] (1095:1095:1095) (1247:1247:1247))
        (PORT d[6] (1212:1212:1212) (1376:1376:1376))
        (PORT d[7] (1188:1188:1188) (1368:1368:1368))
        (PORT d[8] (1396:1396:1396) (1597:1597:1597))
        (PORT d[9] (1138:1138:1138) (1301:1301:1301))
        (PORT d[10] (1180:1180:1180) (1343:1343:1343))
        (PORT d[11] (1143:1143:1143) (1311:1311:1311))
        (PORT d[12] (1150:1150:1150) (1324:1324:1324))
        (PORT clk (1048:1048:1048) (1067:1067:1067))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1048:1048:1048) (1067:1067:1067))
        (PORT d[0] (773:773:773) (856:856:856))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (903:903:903) (1058:1058:1058))
        (PORT clk (1096:1096:1096) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1298:1298:1298) (1504:1504:1504))
        (PORT d[1] (761:761:761) (889:889:889))
        (PORT d[2] (573:573:573) (669:669:669))
        (PORT d[3] (553:553:553) (634:634:634))
        (PORT d[4] (539:539:539) (618:618:618))
        (PORT d[5] (541:541:541) (621:621:621))
        (PORT d[6] (524:524:524) (595:595:595))
        (PORT d[7] (1756:1756:1756) (2036:2036:2036))
        (PORT d[8] (1458:1458:1458) (1658:1658:1658))
        (PORT d[9] (556:556:556) (643:643:643))
        (PORT d[10] (537:537:537) (613:613:613))
        (PORT d[11] (1071:1071:1071) (1229:1229:1229))
        (PORT d[12] (547:547:547) (631:631:631))
        (PORT clk (1094:1094:1094) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (908:908:908) (970:970:970))
        (PORT clk (1094:1094:1094) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1114:1114:1114))
        (PORT d[0] (1192:1192:1192) (1263:1263:1263))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (885:885:885) (1024:1024:1024))
        (PORT d[1] (845:845:845) (971:971:971))
        (PORT d[2] (902:902:902) (1044:1044:1044))
        (PORT d[3] (730:730:730) (864:864:864))
        (PORT d[4] (1137:1137:1137) (1294:1294:1294))
        (PORT d[5] (1107:1107:1107) (1260:1260:1260))
        (PORT d[6] (953:953:953) (1077:1077:1077))
        (PORT d[7] (1005:1005:1005) (1142:1142:1142))
        (PORT d[8] (971:971:971) (1099:1099:1099))
        (PORT d[9] (1145:1145:1145) (1302:1302:1302))
        (PORT d[10] (1184:1184:1184) (1347:1347:1347))
        (PORT d[11] (1116:1116:1116) (1260:1260:1260))
        (PORT d[12] (972:972:972) (1108:1108:1108))
        (PORT clk (1053:1053:1053) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1073:1073:1073))
        (PORT d[0] (890:890:890) (981:981:981))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (586:586:586) (703:703:703))
        (PORT datab (603:603:603) (686:686:686))
        (PORT datac (548:548:548) (654:654:654))
        (PORT datad (627:627:627) (709:709:709))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (511:511:511) (600:600:600))
        (PORT datab (413:413:413) (509:509:509))
        (PORT datac (89:89:89) (110:110:110))
        (PORT datad (90:90:90) (107:107:107))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT dataa (496:496:496) (591:591:591))
        (PORT datab (409:409:409) (490:490:490))
        (PORT datac (604:604:604) (712:712:712))
        (PORT datad (91:91:91) (109:109:109))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
)
